Data packet arithmetic logic devices and methods

ABSTRACT

New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs the PADD operation in about one to two processor clock cycles is disclosed. Also, a new dedicated SMAD logic device that performs a single instruction multiple data add (SMAD) operation in about one to two clock cycles is disclosed.

FIELD

[0001] This disclosure relates generally to data packet manipulation, and specifically, to new instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation, to a new PADD logic device that performs the PADD operation, and to a new SMAD logic device that performs the SMAD operation.

BACKGROUND

[0002] Many applications require the manipulation of data residing in data packets. For instance, packet processing in voice applications require the manipulation of several layers of protocol headers and several types of protocols. Also, protocols such as Internet Protocol (IP), Asynchronous Transfer Mode (ATM), and ATM adaptation layers (AALs) require header manipulation and error detection.

[0003] In the prior art, reduced instruction set computation (RISC) processors are used to perform manipulation of packet data. However, processors typically require many clock cycles to perform complex data manipulation. In addition, because processors typically operate on fixed length words, some inefficiencies result when the data to be manipulated is less than or more than the length of the word.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004]FIG. 1 illustrates a block diagram of an exemplary packet arithmetic logic device in accordance with an embodiment of the invention;

[0005]FIG. 2A illustrates an exemplary syntax for an instruction to perform a packet addition (PADD) in accordance with another embodiment of the invention;

[0006]FIG. 2B illustrates various examples of PADD instructions in accordance with another embodiment of the invention;

[0007]FIG. 3A illustrates an exemplary syntax for an instruction to perform a single multiple data add (SMAD) in accordance with another embodiment of the invention;

[0008]FIG. 3B illustrates various examples of SMAD instructions in accordance with another embodiment of the invention;

[0009]FIG. 4 illustrates diagrams of an exemplary pair of operand packets and a result packet undergoing a packet addition (PADD) function in accordance with another embodiment of the invention;

[0010]FIG. 5 illustrates a block diagram of an exemplary PADD logic device that performs the PADD function in accordance with another embodiment of the invention;

[0011]FIG. 6 illustrates a table listing of exemplary 32-bit length masks used in the exemplary PADD logic device that performs the PADD function in accordance with another embodiment of the invention;

[0012]FIG. 7 illustrates a block diagram of an exemplary single multiple data add (SMAD) logic device in accordance with another embodiment of the invention;

[0013]FIG. 8 illustrates an exemplary block diagram of a 32-bit carry-save adder (CSA) in accordance with an embodiment of the invention;

[0014]FIG. 9 illustrates an exemplary block diagram of a 16-bit CSA in accordance with an embodiment of the invention;

[0015]FIG. 10 illustrates an exemplary block diagram of a 8-bit CSA in accordance with an embodiment of the invention;

[0016]FIG. 11 illustrates an exemplary table illustrating an aspect of the operation of the 32-bit CSA in accordance with an embodiment of the invention;

[0017]FIG. 12 illustrates an exemplary table illustrating an aspect of the operation of the 16-bit CSA in accordance with an embodiment of the invention; and

[0018]FIG. 13 illustrates an exemplary table illustrating an aspect of the operation of the 8-bit CSA in accordance with an embodiment of the invention.

DETAILED DESCRIPTION

[0019] I. Packet Arithmetic Logic Device

[0020]FIG. 1 illustrates a block diagram of an exemplary packet arithmetic logic device 100 in accordance with an embodiment of the invention. The packet arithmetic logic device 100 performs various operations on data packets. Such operations include packet processing for voice applications which require the manipulation of several layers of protocol headers and several types of protocols, and header manipulation and error detection especially in complex protocols such as Internet protocol (IP), asynchronous transfer mode (ATM), and ATM adaptation layers (AALs). The packet arithmetic logic device 100 performs these operations in substantially less clock cycles than the prior art processors which take a multitude of steps to achieve these operations.

[0021] The packet arithmetic logic device 100 comprises an instruction control device 102, a result register RZ 104, a plurality of source data registers RX 106, RY, 108, RX+1 110, and RY+1 112, a data bus 114, a packet add (PADD) logic device 116, and a single instruction multiple data add (SMAD) logic device 118. The instruction control device 102 receives, interprets, and controls the registers and logic devices to properly execute the instruction. The result data register RZ 104 stores the result of the packet arithmetic operations. The source data registers RX 106, RY, 108, RX+1 110, and RY+1 112 store the various operands for the packet arithmetic operations. The PADD logic device 116 performs a packet add operation in about one to two clock cycles. The SMAD logic device 118 performs a multiple data add operation in about one to two clock cycles.

[0022] The following provides various instruction definitions which the packet arithmetic logic device 100 interprets in performing the specified packet arithmetic operations.

[0023] II. Arithmetic Instructions for Packet Processing

[0024] II-A. PADD Instruction

[0025]FIG. 2A illustrates an exemplary syntax for an instruction 200 to perform a packet addition (PADD) in accordance with another embodiment of the invention. In a PADD function, at least a portion of an operand packet X stored in register RX is added with at least another portion of an operand packet Y stored in register RY or an immediate operand to form a result packet Z stored in result register RZ. Optionally, a carry in bit, set by a previous instruction, may be used as a third operand in the addition.

[0026] The PADD instruction 200 defines the result register RZ and one or two source registers RX and RY. The PADD instruction 200 may also define an immediate value as an operand and designated in the instruction as <UI8: immediate>. The PADD instruction 200 may further define the start bit and stop bit of the data field to be modified. These are respectively designated as <UI5: start> and <UI5: stop>. The PADD instruction 200 may also include several control parameters, including a control parameter designated as [−C] to indicate an addition with a carry in, a control parameter designated as [−M] to indicate a modulo 2^(n)−1 addition, a control parameter designated as −N to indicate an addition affecting only the specified data field, and a control parameter designated as −I to indicate that the second operand is supplied as an immediate value.

[0027]FIG. 2B illustrates various examples of PADD instructions 250 in accordance with another embodiment of the invention. In the first example instruction:

[0028] PADD RZ, RX, RY

[0029] the instruction control device 102 causes the PADD logic device 116 to add the operand X stored in the source register RX 106 to the operand Y stored in the source register RY 108, and place the result Z in the result register RZ 104 (i.e. RZ=RX+RY).

[0030] In the second example instruction:

[0031] PADD −C RZ, RX, RY

[0032] the instruction control device 102 causes the PADD logic device 116 to add the operand X stored in the source register RX 106, the operand Y stored in the source register RY 108, and the carry in from a previous instruction, and place the result Z in the result register RZ 104 (i.e. RZ=RX+RY+Cin).

[0033] In the third example instruction:

[0034] PADD −I RZ, RX, <UI8: immediate>

[0035] the instruction control device 102 causes the PADD logic device 116 to add the operand X stored in the source register RX 106 to an immediate value specified in <UI8: immediate>, and place the result Z in the result register RZ 104 (i.e. RZ=RX+<immediate>).

[0036] In the fourth example instruction:

[0037] PADD −N RZ, RX, RY <UI5: start>, <UI5: stop>

[0038] the instruction control device 102 causes the PADD logic device 116 to add the data field beginning at the start bit and ending at the stop bit of operand X stored in the source register RX 106 to the data field beginning at the least significant bit and having a length defined as stop-start+1 in the operand Y stored in the source register RY 108, and place the result data field in the same bit position defined by the start and stop in the result Z stored in the result register RZ. The remaining data fields of operand X stored in source register RX 106 outside of the specified data field are copied bitwise to the result Z stored in result register RZ. (i.e. RZ={RX[31:stop], (RX[stop:start]+RY[length]) modulo 2 ^(length), RX[start:0]}).

[0039] In the fifth example instruction:

[0040] PADD −M RZ, RX, RY

[0041] the instruction control device 102 causes the PADD logic device 116 to modulo 2 ^(n)−1 add the operand X stored in the source register RX 106 to the operand Y stored in the source register RY 108, and place the result Z in the result register RZ 104 (i.e. RZ=(RX+RY) modulo 2 ^(n) −1).

[0042] In the sixth example instruction:

[0043] PADD −N −I RZ, RX, <UI8:immediate>, <UI5: start>

[0044] the instruction control device 102 causes the PADD logic device 116 to add the data field beginning at the start bit and ending at the most significant bit of operand X stored in the source register RX 106 to the data field beginning at the least significant bit and ending at the bit 31—start bit of the immediate value, and place the result data field in the same bit position defined by the start and most significant bit of the result Z stored in the result register RZ 104. The remaining data field of operand X stored in source register RX 106 outside of the specified field is copied bitwise to the result Z stored in result register RZ 104. (i.e. RZ={(RX[31:start]+immediate[31-start:0]) modulo 2 ^(31−start+), RX[start:0]}).

[0045] II-B. SMAD Instruction

[0046]FIG. 3A illustrates an exemplary syntax for an instruction 300 to perform a single instruction multiple data add (SMAD) in accordance with another embodiment of the invention. In a SMAD function, multiple operands are added together. For instance, if 32-bit addition is to be performed, up to four 32-bit operands X, Y, X+1, and Y+1 stored respectively in registers RX 106, RY 108, RX+1 110, and RY+1 112 may be added to form result Z stored in result register RZ 104. If 16-bit addition is to be performed, up to eight 16-bit operands X[15:0], X[31:16], Y[15:0], Y[31:16], X+1[15:0], X+1[31:16], Y+1[15:0], and Y+1[31:16] stored respectively as pairs in registers RX 106, RY 108, RX+1 110 and RY+1 112 may be added to form result Z stored in result register RZ 104. If 8-bit addition is to be performed, up to 16 8-bit operands X[7:0], X[15:8], X[23:16], X[31:24], Y[7:0], Y[15:8], Y[23:16], Y[31:24], X+1[7:0], X+1[15:8], X+1[23:16], X+1[31:24], Y+1[7:0], Y+1[15:8], Y+1[23:16], Y+1[31:24] stored respectively as quads in registers RX 106, RY 108, RX+1 110 and RY+1 112 may be added to form result Z stored in result register RZ 104.

[0047] The SMAD instruction 300 defines the result register RZ and one or two source registers RX and RY. The SMAD instruction 300 may also include several control parameters, including a control parameter designated as [−A] to indicate that the result is accumulated into the result register RZ, and a control parameter designated as [−M] to indicate a modulo 2 ^(n)−1 addition. The SMAD instruction 300 may also include a parameter designated as <UI2: Length> that indicates the data width of the operands (e.g. 0 indicates 8-bit operand, 1 indicates 16-bit operands, and 2 indicates 32-bit operands). In addition, the SMAD instruction 300 may include a parameter designated as <UI2: Num Ops> to indicate the number of operands to be used in the addition (e.g. 0 indicates two source operands RX and RY, 1 indicates three source operands RX, RX+1, and RY, 2 indicates three source operands RX, RY, and RY+1, and 4 indicates four operands RX, RY, RX+1, and RY+1).

[0048]FIG. 3B illustrates various examples of SMAD instructions 350 in accordance with another embodiment of the invention. In the first example instruction:

[0049] SMAD RZ, RX, RY, 2,0

[0050] the instruction control device 102 causes the SMAD logic device 118 to add the 32-bit operand X stored in the source register RX 106 to the 32-bit operand Y stored in the source register RY 108, and place the result Z in the result register RZ 104 (i.e. RZ=RX+RY).

[0051] In the second example instruction:

[0052] SMAD −A RZ, RX, RY

[0053] the instruction control device 102 causes the SMAD logic device 118 to add the 32-bit operand X stored in the source register RX 106, the 32-bit operand Y stored in the source register RY 108, and the 32-bit operand Z stored in the result register RZ 104, and place the result Z in the result register RZ 104 (i.e. RZ=RZ+RX+RY).

[0054] In the third example instruction:

[0055] SMAD RZ, RX, RY, 2, 3

[0056] the instruction control device 102 causes the SMAD logic device 118 to add the 32-bit operand X stored in the source register RX 106, the 32-bit operand Y stored in the source register RY 108, the 32-bit operand X+1 stored in the source register RX+1 110, and the 32-bit operand Y+1 stored in the source register RY+1 112, and place the result Z in the result register RZ 104 (i.e. RZ=RX+RY+RX+1+RY+1).

[0057] In the fourth example instruction:

[0058] SMAD RZ, RX, RY, 0, 0

[0059] the instruction control device 102 causes the SMAD logic device 118 to add the 8-bit operand X[7:0] stored in the source register RX[7:0] 106, the 8-bit operand X[15:8] stored in the source register RX[15:8] 106, the 8-bit operand X[23:16] stored in the source register RX[23:16] 106, the 8-bit operand X[31:24] stored in the source register RX[31:24] 106, the 8-bit operand Y[7:0] stored in the source register RY[7:0] 108, the 8-bit operand Y[15:8] stored in the source register RY[15:8] 108, the 8-bit operand Y[23:16] stored in the source register RY[23:16] 108, and the 8-bit operand Y[31:24] stored in the source register RY[31:24] 108, and place the result Z in the result register RZ 104 (i.e. RZ=RX[7:0]+RX[15:8]+RX[23:16]+RX[31:24]+RY[7:0]+RY[15:8]+RY[23:16]+RY[31:24]).

[0060] In the fifth example instruction:

[0061] SMAD −M RZ, RX, RY, 2, 0

[0062] the instruction control device 102 causes the SMAD logic device 118 to modulo 2 ^(n)−1 add the 32-bit operand X stored in the source register RX 106 to the 32-bit operand Y stored in the source register RY 108, and place the result Z in the result register RZ 104 (i.e. RZ=(RX+RY) modulo 2 ^(n)−1).

[0063] In the sixth example instruction:

[0064] PADD −A −M RZ, RX, RY, 2, 0

[0065] the instruction control device 102 causes the SMAD logic device 118 to modulo 2 ^(n)−1 add the 32-bit operand X stored in the source register RX 106, the 32-bit operand Y stored in the source register RY 108, and the 32-bit operand Z stored in the result register RZ 104, and place the result Z in the result register RZ 104 (i.e. RZ=(RZ+RX+RY) modulo 2 ^(n)−1).

[0066] I. The PADD Logic Device

[0067]FIG. 4 illustrates diagrams of exemplary pair of operand packets and a result packet undergoing a packet addition (PADD) function in accordance with another embodiment of the invention. In a PADD function, an operand data field in an operand packet X is to be added with another operand data field in operand packet Y to form a data field in a result packet Z. The operand data field in the operand packet X has a length of n bits and its least significant bit is situated m bits from the least significant bit of the operand packet X. The operand data field in the operand packet Y also has a length of n bits and its least significant bit coincides with the least significant bit of the operand packet Y. The result data field in the result packet Z has a length of n bits and its least significant bit is situated m bits from the least significant bit of the operand packet Z. The remaining data fields in the operand packet X are copied bitwise to the result packet Z.

[0068] For example, operand data Field X−2 in operand packet X, which has a length of n bits and its least significant bit is situated m bits from the least significant bit of the operand packet X, is added to operand data Field Y−1 which also has a length of n bits and its least significant bit coincides with the least significant bit of the operand packet Y. The result data field Z−2, being the addition of Fields X−2 and Field Y−1, has a length of n bits and its least significant bit is situated m bits from the least significant bit of the operand packet Z. The remaining data Fields X−1 and X−3 in the operand packet X are copied bitwise to data Fields Z−1 and Z−3 of the result packet Z.

[0069]FIG. 5 illustrates a block diagram of an exemplary PADD logic device 500 that performs the PADD function in accordance with another embodiment of the invention. The PADD logic device 500 comprises a left shifter 502, bitwise logic ORs 504 and 514, bitwise logic ANDs 506, 510 and 512, and an adder 508. The operand Y is applied to the input of the left shifter 502 and the number m controls the amount of left shifting of the left shifter 502. The output of the left shifter 502 is applied to an input of the bitwise OR 504.

[0070] A mask (m+n) as listed in the table shown in FIG. 6 is applied to the other input of the bitwise OR 504, to an inverted input of bitwise AND 506, to an inverted input of bitwise AND 510, and to an input of bitwise AND 512. If the carry-in C_(in) is 1, the left shifter 502 shifts in logic ones at its least significant bits, otherwise it shifts logic zeros. The operand X is applied to the respective inputs of the bitwise ANDs 506 and 512. The outputs of the bitwise OR 504 and bitwise AND 506 are applied to the inputs of adder 508. The output of the adder 508 is applied to the input of bitwise AND 510. The outputs of bitwise ANDs 510 and 512 are applied to the inputs of bitwise OR 514. And, the output of bitwise OR 514 generates the result packet Z.

[0071] The bitwise OR logic device 504 generates an intermediate packet 550 comprising the operand data Field Y−1 situated at the same bit position as the operand data Field X−1, with logic ones on the more significant bit side of the Field Y−1, and with either all logic ones if the carry-in C_(in) is asserted or all logic zeros if the carry-in C_(in) is not asserted on the lesser significant bit side of the Field Y−1. Thus, the following relationship holds for the output of the bitwise OR logic device 504:

[0072] Field X−3 Field X−2 Field X−1 Operand X

[0073] 1 . . . 1 Field Y−1 0 . . . 0 Intermediate Packet 550 C_(in)=0

[0074] 1 . . . 1 Field Y−1 1 . . . 1 Intermediate Packet 550 C_(in)=1

[0075] The intermediate packet 550 having logic ones at the same bit position as Field X−1 allows the carry-in to propagate to the sum field X+Y.

[0076] The bitwise AND logic device 506 generates an intermediate packet 552 which comprises logic zeros at the bit position of Field X−3 and Fields X−2 and X−1 at the same bit position as the corresponding Fields X−2 and X−1 of the operand packet X. Thus, the following relationship holds for the output of the bitwise AND logic device 506:

[0077] Field X−3 Field X−2 Field X−1 Operand X

[0078] 0 . . . 0 Field X−2 Field X−1 Intermediate Packet 552

[0079] The output of the adder 508 generates an intermediate packet 554 which comprises don't cares x at the same bit position as Field X−3, the sum Field X+Y at the same bit position as Field X−2, and the Field X−1 at the same bit position as Field X−1. Thus, the following relationship holds for the output of the adder 508:

[0080] Field X−3 Field X−2 Field X−1 Operand X

[0081] x . . . x Field X+Y Field X−1 Intermediate Packet 554

[0082] The bitwise AND logic device 510 generates an intermediate packet 556 which comprises logic zeros at the same bit position as Field X−3, the sum Field X+Y at the same bit position as Field X−2, and the Field X−1 at the same bit position as Field X−1. Thus, the following relationship holds for the output of the bitwise AND logic device 510:

[0083] Field X−3 Field X−2 Field X−1 Operand X

[0084] 0 . . . 0 Field X+Y Field X−1 Intermediate Packet 556

[0085] The bitwise AND logic device 512 generates an intermediate packet 558 which comprises Field X−3 at the same bit position as Field X−3 and logic zeros at the same bit position as Fields X−1 and X−2. Thus, the following relationship holds for the output of the bitwise AND logic device 512:

[0086] Field X−3 Field X−2 Field X−1 Operand X

[0087] Field X−3 Field 0 . . . 0 Intermediate Packet 558

[0088] The bitwise OR logic device 514 bitwise ORs the outputs of the bitwise AND logic device 510 and 512 to generate the result packet Z.

[0089] The following operand packets and result packet serves as an example to illustrate the operation of the PADD logic device 500:

[0090] 0 . . . 111101101001101011010 Operand X

[0091] 0 . . . 00000000000000011001 Operand Y

[0092] 0 . . . 11101110110001011010 Result Z

[0093] m=8, n=8, C_(in)=0

[0094] As discussed above, the operand Y is applied to the input of the left shifter 502, the number m controls the amount of left shifting, and the carry-in C_(in) causes the left shifter 502 to shift in logic ones if it is asserted and logic zeros if it is not asserted. In this example, the number m is eight (8) and the C_(in) is a logic zero (0). Therefore, the left shifter 502 left shifts the operand Y by eight (8) bits and shifts in logic zeros (0s). Accordingly, the output of the left shifter 502 is as follows:

[0095] 0 . . . 00000001100100000000 (i.e. 0 . . . 000 Field Y−1 00000000)

[0096] Referring to both FIGS. 5 and 6, in this example the number (m+n) is equal to 16. Therefore, according to the table, the mask and its complement are given by the following:

[0097] mask=1 . . . 11100000000000000000

[0098] complement mask=0 . . . 00011111111111111111

[0099] The output of the bitwise OR 504, being the bitwise OR of the output of the left shifter 502 and the mask, is given by the following:

[0100] 1 . . . 111000001100100000000 (i.e. 1 . . . 111 Field Y−1 00000000)

[0101] The output of the bitwise AND 506, being the bitwise AND of the complement mask and the operand X, is given by the following:

[0102] 0 . . . 000001101001101011010 (i.e. 0 . . . 000 Field X−2 Field X−1)

[0103] The outputs of the bitwise OR 504 and the bitwise AND 506 are summed by the adder 508. Since the carry-in C_(in) is a logic zero, the output of the adder 508 is given by the following:

[0104] 1 . . . 11111110010001011010 (i.e. 1 . . . 111 Field X+Y Field X−1)

[0105] The output of the adder 508 and the complement mask are bitwise AND by bitwise AND logic device 510. Therefore, the output of the bitwise AND logic device 510 is given by the following:

[0106] 0 . . . 000001110010001011010 (i.e. 0 . . . 000 Field X+Y Field X−1)

[0107] The output of the bitwise AND 512, being the bitwise AND of the complement mask and the operand X, is given by the following:

[0108] 0 . . . 111100000000000000000 (i.e. Field X−3 0000000000000000)

[0109] The output of the bitwise OR logic device 514, which is the bitwise OR of the output of the bitwise AND logic devices 510 and 512, is given by the following:

[0110] 0 . . . 111101110110001011010 (i.e. Field X−3 Field X+Y Field X−1)

[0111] which is the result packet Z.

[0112] An advantage of the PADD logic device 500 is that it performs the PADD operation relatively fast and efficient. In the prior art, RISC processors are employed to perform the PADD operation. However, RISC processors need to perform many logic operations to perform the PADD operation. This requires the RISC processors to take numerous clock cycles to perform the operation. With the PADD logic device 500, only one or two processor cycles are used to attain the PADD result.

[0113] II. Modulo 2^(n)/Modulo 2^(n)−1 Addition

[0114]FIG. 7 illustrates a block diagram of an exemplary single multiple data add (SMAD) logic device 700 in accordance with another embodiment of the invention. The SMAD logic device performs the modulo 2 ^(n) and/or the modulo 2 ^(n)−1 of up to four 32-bit numbers, eight 16-bit numbers, or 16 8-bit numbers. The SMAD logic device 700 comprises a 32-bit carry-save adder (CSA) 702, a 16-bit CSA 704, and a 8-bit CSA 706. The SMAD logic device 700 further comprises a 6-input/2-output multiplexer 708, a first 32-bit adder 710, a second 32-bit adder 712, 2-input/1-output multiplexers 714, 716, and 718, and 3-input/1-output multiplexer 720.

[0115] The 32-bit CSA 702 receives up to four 32-bit operands X₀[31:0], X₁[31:0], Y₀[31:0], and Y₁[31:0], and generates a carry C<32:0> and a save S<31:0>. The 32-bit CSA 702 comprises 32 4:2 compressors 702-0 through 702-31. Each of the 4:2 compressors, represented as 702-n, receives as inputs X₀[n], X₁[n], Y₀[n], and Y₁[n], and generates the carry C<n> and save S<n>. The carry of compressor 702-n is allowed to carry to the first compressor 702-0 except under certain circumstances with regard to modulo 2 ^(n) addition, as will be explained further below.

[0116] The 16-bit CSA 704 receives four operands C<31:16>, C<15:1>, S<31:16>, and S<15:0> from the carry C<31:0> and the save S<31:0> of the 32-bit CSA 702 if 16-bit addition is being performed, and generates carry C1<15:1> and save S1<15:0>. The 16-bit CSA 704 comprises 16 4:2 compressors 704-0 through 704-15. Each of the 4:2 compressors, represented as 704-n, receives as inputs C<n>, S<n> except that of C<0> which instead receives a logic zero, and generates the carry C1<n> and save S1<n>. The carry of compressor 704-n is allowed to carry to the first compressor 704-0 except under certain circumstances with regard to modulo 2 ^(n) addition, as will be explained further below.

[0117] The 8-bit CSA 706 receives four operands C1<15:8>, C1<7:1>, S1<15:8>, and S1<7:0> from the carry C1<15:1> and the save S1<15:0> of the 16-bit CSA 704 if 8-bit addition is being performed, and generates carry C2<7:1> and save S2<7:0>. The 8-bit CSA 706 comprises eight 4:2 compressors 706-0 through 706-7. Each of the 4:2 compressors, represented as 706-n, receives as inputs C1<n>, S1<n> except that of C1<0> which instead receives a logic zero, and generates the carry C2<n> and save S2<n>. The carry of compressor 706-n is allowed to carry to the first compressor 706-0 except under certain circumstances with regard to modulo 2 ^(n) addition, as will be explained further below.

[0118] The six inputs to the 6-input/2-output multiplexer 708 include {24′hffffff, C2<7:1>, C<32>}, {16′hffff, C1<15:1>, C<32>}, {C<31:1>, C<32>}, {24′h0, S2<7:0>}, {16′h0, S1<15:0>}, and S<31:0>. If 32-bit addition is being performed, the multiplexer 708 selects as its outputs C<31:0> and S<31:0>. If 16-bit addition is being performed, the multiplexer 708 selects as its outputs {16′hffff, C1<15:1>, C<32>} and {16′h0, S1<15:0>}. If 8-bit addition is being performed, the multiplexer 708 selects as its outputs {24′hffffff, C2<7:1>, C<32>} and {24′h0, S2<7:0>}.

[0119] The outputs of the multiplexer 708 are applied in parallel to the respective inputs of the first and second 32-bit adders 710 and 712. The first 32-bit adder 710 has a logic zero as a carry-in C_(in). The carry-out C_(out) off the first 32-bit adder 710 controls the multiplexers 714, 716, and 718 in a manner that if the carry-out C_(out) is asserted, the multiplexers 714, 716, and 718 select the corresponding sum_(—)1 input, otherwise it selects the corresponding sum_(—)0 input. The first 32-bit adder generates the sum_(—)0 output, which is applied to the corresponding inputs of multiplexers 714, 716, and 718 if 8-bit, 16-bit, or 32-bit addition respectively is performed.

[0120] The second 32-bit adder 712 has a logic one as a carry-in C_(in), and generates the sum_(—)1 output, which is applied to the corresponding inputs of multiplexers 714, 716, and 718 if 8-bit, 16-bit, or 32-bit addition respectively is performed. The outputs of the multiplexers 714, 716, and 718 are applied to the inputs of the 3-input/1-output multiplexer 720. If 8-bit addition is being performed, the multiplexer 720 selects as its output the output of multiplexer 714. If 16-bit addition is being performed, the multiplexer 720 selects as its output the output of multiplexer 716. If 32-bit addition is being performed, the multiplexer 720 selects the output of multiplexer 718. The output of the multiplexer 720 is the result Z<31:0> of the modulo 2 ^(n) or modulo 2 ^(n)−1 addition of the input operands. The following explains, in more detail, the various additions and operands that the modulo logic device 700 performs.

[0121]FIG. 8 illustrates an exemplary block diagram of a 32-bit carry-save adder (CSA) 702 in accordance with an embodiment of the invention. As previously discussed with reference to FIG. 7, the 32-bit CSA 700 comprises 32 4:2 compressors 702-0 sequentially through 702-31. The inputs to the 4:2 compressor 702-n includes operands y[n], y1[n], x[n], and x1[n]. The 4:2 compressor 702-n generates carry c[n] and save s[n]. The carry-out co_<n+1> of 4:2 compressor 702-n is coupled to the carry-in of 4:2 compressor 702-<n+1>, except that of compressor 702-31 whose carry-out is coupled to the carry-in of 4:2 compressor 702-0.

[0122]FIG. 9 illustrates an exemplary block diagram of a 16-bit carry-save adder (CSA) 704 in accordance with an embodiment of the invention. As previously discussed with reference to FIG. 7, the 16-bit CSA 704 comprises 16 4:2 compressors 704-0 sequentially through 704-15. The inputs to the 4:2 compressor 704-n include the output carry and save from the 32-bit CSA 702, such as s<n+16>, c<n+16>, s<n>, and c<n> except the first compressor 704-0 which has as inputs c<16>, s<16>, s<0>, and co1<16> from the carry out of the last compressor 704-15. The 4:2 compressor 704-n generates carry c1<n> and save s1<n>. The carry-out co1_<n+1> of 4:2 compressor 704-n is coupled to the carry-in of 4:2 compressor 704-<n+1>, except that of compressor 704-15 whose carry-out co1_(—)16 is coupled to the carry-in of 4:2 compressor 704-0.

[0123]FIG. 10 illustrates an exemplary block diagram of a 8-bit carry-save adder (CSA) 706 in accordance with an embodiment of the invention. As previously discussed with reference to FIG. 7, the 8-bit CSA 706 comprises eight (8) 4:2 compressors 706-0 sequentially through 706-7. The inputs to the 4:2 compressor 706-n include the output save and carry from the 16-bit CSA 702, namely s1<n+8>, c1<n+8>, s1<n>, and c1<n> except the first compressor 706-0 which has as inputs s1<8>, c1<8>, s1<0>, and c2<8> from the carry of the last compressor 706-7. The 4:2 compressor 706-n generates carry c1<n> and save s1<n>. The carry-out co2_<n+1> of 4:2 compressor 706-n is coupled to the carry-in of 4:2 compressor 706-<n+1>, except that of compressor 706-7 whose carry-out co2_(—)8 is coupled to the carry-in of 4:2 compressor 706-0.

[0124] II-A 32-Bit Operands Modulo 2^(n) Addition

[0125] With reference to the table illustrated in FIG. 11, if the 32-bit operands X₀[31:0], X₁[31:0], Y₀[31:0], and Y₁[31:0] are applied to the 32-bit CSA 702, the carry-out co_(—)32 of the last 4:2 compressor 702-31 does not propagate to the carry-in of the first 4:2 compressor 702-0. In addition, the carry C<32> of the last 4:2 compressor does not propagate to the multiplexer 708. Since this is a 32-bit operation, the multiplexer 708 selects as its outputs the carry C<31:1> and save S<31:0>. Accordingly, the carry C<31:1> and save S<31:0> are summed by the first adder 710 to generate sum_(—)0. The second adder 712 is ignored in modulo 2^(n) addition. The multiplexer 718 selects as its output the sum_(—)0 for modulo 2^(n) addition. Since, again this is a 32-bit operation, the multiplexer 720 selects the output of the multiplexer 718. The output of the multiplexer 720 is the modulo 2^(n) addition of the operands X₀[31:0], X₁ [31:0], Y₀[31:0], and Y₁ [31:0].

[0126] II-B 32-Bit Operands Modulo 2^(n)−1 Addition

[0127] In the case of modulo 2 ^(n)−1 addition of 32-bit operands X₀[1:0], X₁[31:0], Y₀[31:0], and Y₁[31:0], the carry-out of the last compressor 4:2 702-31 of the 32-bit CSA propagates to the carry-in of the first 4:2 compressor 702-0. In addition, the carry C[32] of the last 4:2 compressor 702-31 propagates to the multiplexer 708. Since this is a 32-bit operation, the multiplexer 708 selects as its outputs the {C<31:1>, C<32>} and save S<31:0>. Accordingly, the {C<3 1:1>, C<32>} and S<31:0> are summed by both the first and second adders 710 and 712 to generate respectively sum_(—)0 and sum_(—)1. If the carry out C_(out) of the first adder 710 is a logic one, the multiplexer 718 selects as its output the sum_(—)1, otherwise it selects the sum_(—)0. Since, again this is a 32-bit operation, the multiplexer 720 selects the output of the multiplexer 718. The output of the multiplexer 720 is the modulo 2^(n)−1 addition of the operands X₀[31:0], X₁[31:0], Y₀[^(31:0)], and Y₁ [31:0].

[0128] II-C 16-Bit Operands Modulo 2^(n) Addition

[0129] With reference to the table illustrated in FIG. 11, if eight (8) 16-bit operands X₀[15:0], X₀[31:16], X₁[15:0], X₁[31:16], Y₀[15:0], Y₀[31:16], Y₁[15:0], and Y₁[31:16] are applied to the 32-bit CSA 702, the carry-outs co_(—)16 and co _(—)32 of the 16^(th) and last 4:2 compressors 702-15 and 702-31 do not propagate respectively to the carry-ins of the 17^(th) and first 4:2 compressors 702-16 and 702-0. In addition, the carrys C<16> and C<32> generated by the 16^(th) and last compressors 702-15 and 702-31 do not propagate to an input of the first compressor 704-0 of the 16-bit CSA 704 and to the multiplexer 708, respectively.

[0130] The carries C<31:16> and C<15:1,0> and saves S<31:16> and S<15:0> generated by the 32 bit- CSA 702 are applied to the 16-bit CSA 704, which generates carry C1<15:1,0> and save S1<15:0>. As shown in the table illustrated in FIG. 12, the carry-out co1_(—)16 and carry C1<16> of the last 4:2 compressor 704-15 do not propagate to the first 4:2 compressor 704-0.

[0131] Since this is a 16-bit operation, the multiplexer 708 selects as its outputs the {16′hffff, C1<15:1>, C<32>} and {16′h0, S1<15:0>}. Accordingly, the {16′hffff, C1<15:1>, C<32>} and {16′h0, S1<15:0>} are summed by the first adder 710 to generate sum_(—)0. The second adder 712 is ignored in modulo 2^(n) addition. The multiplexer 716 selects as its output the sum_(—)0<15:0> for modulo 2^(n) addition. Since, again this is a 16-bit operation, the multiplexer 720 selects the output of the multiplexer 716. The output of the multiplexer 720 is the modulo 2^(n) addition of the operands X₀[15:0], X₀[31:16], X₁[15:0], X₁[31:16], Y₀[15:0], Y₀[31:16], Y₁[15:0], and Y₁[31:16].

[0132] II-D 16-Bit Operands Modulo 2^(n)−1 Addition

[0133] In the case of Modulo 2^(n)−1 addition of eight (8) 16-bit operands X₀[15:0], X₀[31:16], X₁[15:0], X₁[31:16], Y₀[15:0], Y₀[31:16], Y₁[15:0], and Y₁[31:16], the carry-outs co_(—)16 and co_(—)32 of the 16^(th) and last 4:2 compressors 702-15 and 702-31 propagate respectively to the carry-ins of the 17^(th) and first 4:2 compressors 702-16 and 702-0. In addition, the carries c<16> and c<31> generated by the 16 ^(th) and last compressors 702-15 and 702-31 propagate to an input of the first compressor 704-0 of the 16-bit CSA 704 and to the multiplexer 708, respectively.

[0134] The carries C<31:16> and C<15:1,0> and saves S<31:16> and S<15:0> generated by the 32-bit CSA 702 are applied to the 16-bit CSA 704, which generates carry C1<15:1,0> and save S1<15:0>. The carry-out co1_(—)16 and carry c1<16> of the last 4:2 compressor 704-15 propagate to the carry-in and input of the first 4:2 compressor 704-0 in modulo 2^(n)−1 addition.

[0135] Since this is a 16-bit operation, the multiplexer 708 selects as its outputs the {16′hffff, C1<15:1>, C<32>} and {16′h0, S1<15:0>}. Accordingly, the {16′hffff, C1<15:1>, C<32>} and {16′ho, S1<15:0>} are summed by the first and second adders 710 and 712 to generate respectively sum_(—)0<15:0> and sum_(—)1<15:0>. If the carry out C_(out) of the first adder 710 is a logic one, the multiplexer 716 selects as its output the sum_(—)1<15:0>, otherwise it selects the sum_(—)0<15:0>. Since, again this is a 16-bit operation, the multiplexer 720 selects the output of the multiplexer 716. The output of the multiplexer 720 is the modulo 2^(n)−1 addition of the operands X₀[15:0], X₀[31:16], X₁[15:0], X₁[31:16], Y₀[15:0], Y₀[31:16], Y₁[15:0], and Y₁[31:16].

[0136] II-E 8-Bit Operands Modulo 2^(n) Addition

[0137] With reference to the table illustrated in FIG. 11, if the 16 8-bit operands X₀[7:0], X₀[15:8], X₀[23:16], X₀[31:24], X₁[7:0], X₁[15:8], X₁[23:16], X₁[31:24], Y₀[7:0], Y₀[15:8], Y₀[23:16], Y₀[31:24], Y₁[7:0], Y₁[15:8], Y₁[23:16], and Y₁[31:24] applied to the 32-bit CSA 702 are to be modulo 2^(n) added, the carry-outs c0_(—)8, c0_(—)16, co_(—)24 and co_(—)32 of 4:2 compressors 702-7, 702-15, 702-23, and 702-31 do not propagate respectively to the carry-ins of 4:2 compressors 702-8, 702-16, 702-24, and 702-0. In addition, the carries c<8>, c<16>, c<24>, and c<32> of respectively 4:2 compressors 702-7, 702-15, 702-23, and 702-31 do not propagate respectively to the inputs to the 4:2 compressors 704-8, 704-0 and 704-8, and multiplexer 708.

[0138] The carries C<7:1, 0>, C<15:8>, C<23:16> and C<31:24>, and saves S<7:0>, S<15:8>, S<23:16> and S<31:24> are applied to the 16-bit CSA 704, which generates carries C1<7:1,0> and C1<15:8> and saves S1<7:0> and S1<15:8>. With reference to the table illustrated in FIG. 12, the carry-outs co1_(—)8 and co1_(—)16 of 4:2 compressors 704-7 and 704-15 do not propagate respectively to 4:2 compressors 704-8 and 704-0. In addition, the carrys c1<8> and c1<16> of the 4:2 compressors 704-7 and 704-16 do not propagate respectively to 4:2 compressors 706-0 and 704-0.

[0139] The carries C1<7:1,0> and C1<15:8> and saves S1<7:0> and S1<15:8> are applied to the 8-bit CSA 706, which generates carry C2<7:1,0> and save S2<7:0>. With reference to the table illustrated in FIG. 13, the carry-out co2_(—)8 and carry c2<8> of the last 4:2 compressor 706-7 do not propagate to the carry-in and input of the first compressor 706-0.

[0140] Since this is an 8-bit operation, the multiplexer 708 selects as its outputs the {24′hffff, c2<7:1>, c<32>} and {24′h0, S2<7:0>}. Accordingly, the {24′hffff, c2<7:1>, c<32>} and {24′h0, S2<7:0>} are summed by the first adder 710 to generate sum_(—)0<7:0>. The second adder 712 is ignored in modulo 2^(n) addition. The multiplexer 714 selects as its output the sum_(—)0<7:0> for modulo 2^(n) addition. Since, again this is an 8-bit operation, the multiplexer 720 selects as its output the output of the multiplexer 714. The output of the multiplexer 720 is the modulo 2^(n) addition of the operands X₀[7:0], X₀[15:8], X₀[23:16], X₀[31:24], X₁[7:0], X₁[15:8], X₁[23:16], X₁[31:24], Y₀[7:0], Y₀[15:8], Y₀[23:16], Y₀[31:24], Y₁[7:0], Y₁[15:8], Y₁[23:16], and Y₁[31:24].

[0141] II-F 8-Bit Operands Modulo 2^(n) −1 Addition

[0142] In the case of Modulo 2^(n)−1 addition of 16 8-bit operands X₀[7:0], X₀[15:8], X₀[23:16], X₀[31:24], X₁[7:0], X₁[15:8], X₁[23:16], X₁[31:24], Y₀[7:0], Y₀[15:8], Y₀[23:16], Y₀[31:24], Y₁[7:0], Y₁[15:8], Y₁[23:16], and Y₁[31:24], the carry-outs co_(—)8, co_(—)16, co_(—)24, and co_(—)32 of 4:2 compressors 702-7, 702-15, 702-23, and 702-31 do propagate respectively to the carry-ins of 4:2 compressors 702-8, 702-16, 702-24 and 702-0. Also, the carries c<8>, c<16>, c<24>, and c<32> do propagate respectively to the inputs of 4:2 compressors 704-8, 704-0, and 704-8, and to multiplexer 708.

[0143] The carries C<7:1, 0>, C<15:8>, C<23:16> and C<31:24>, and saves S<7:0>, S<15:8>, S<23:16> and S<31:24> are applied to the 16-bit CSA 704, which generates carries C1<7:1,0> and C1<15:8> and saves S1<7:0> and S1<15:8>. With reference to the table illustrated in FIG. 12, the carry-outs co1_(—)8 and co1_(—)16 of 4:2 compressors 704-7 and 704-15 do propagate to 4:2 compressors 704-8 and 704-0. The carries C1<7:1,0> and C1<15:8> and saves S1<7:0> and S1<15:8> are applied to the 8-bit CSA 706, which generates carry C2<7:1,0> and save S2<7:0>. With reference to the table illustrated in FIG. 13, the carry-out co2_(—)8 and carry c2<8> of the last 4:2 compressor 706-7 do propagate to the inputs of 4:2 compressor 706-0. The carry C2<7:1,0> and save S2<7:0> are applied to the multiplexer 708.

[0144] Since this is an 8-bit operation, the multiplexer 708 selects as its outputs the {24′hffffff, c2<7:1>, c<32>}, and {24′h0, S2<7:0>}. Accordingly, the {24′hffffff, c2<7:1>, c<32>}, and {24′h0, S2<7:0>} are summed by the first and second adders 710 and 712 to generate respectively sum_(—)0<7:0> and sum_(—)0<7:0>. If the carry out C_(out) of the first adder 710 is a logic one, the multiplexer 714 selects as its output the sum_(—)1<7:0>, otherwise it selects the sum_(—)0<7:0>. Since, again this is an 8-bit operation, the multiplexer 720 selects as its output the output of the multiplexer 714. The output of the multiplexer 720 is the modulo 2^(n) addition of the operands X₀[7:0], X₀[15:8], X₀[23:16], X₀[31:24], X₁[7:0], X₁[15:8], X₁[23:16], X₁[31:24], Y₀[7:0], Y₀[15:8], Y₀[23:16], Y₀[31:24], Y₁[7:0], Y₁[15:8], Y₁[23:16], and Y₁[31:24].

[0145] II-G Conclusion—Modulo 2^(n)/Modulo 2^(n)−1 Addition

[0146] The modulo logic device 700 enables practical realization of implementing the SMAD/ESMAD functions. In the prior art, achieving the SMAD/ESMAD functions is typically done by executing a series of instruction by a processor. These instructions include a number of adds and logical operations, which can consume several to many clock processor cycles. The modulo logic device 700 can perform the SMAD/ESMAD functions within one or two processor cycles for substantial speedup in performance over executing instructions.

[0147] In the foregoing specification, this disclosure has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the embodiments of the embodiments of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. 

It is claimed:
 1. A method comprising: receiving a PADD instruction comprising a result register identifier to identify a result register, a first source register identifier to identify a first source register storing a first operand, and an operand identifier to identify a second operand; and in response to receiving said PADD instruction, causing a dedicated PADD logic device to perform a packet addition of the first and second operands to generate a result, and to subsequently store the result in said result register.
 2. The method of claim 1, wherein said operand identifier identifies a second source register storing said second operand.
 3. The method of claim 1, wherein said operand identifier identifies an immediate value to use as said second operand.
 4. The method of claim 1, wherein said PADD instruction further comprises a start identifier to identify the start bit of said first operand.
 5. The method of claim 1, wherein said PADD instruction further comprises a stop identifier to identify the stop bit of said first operand.
 6. The method of claim 1, wherein said PADD instruction includes a carry in parameter to cause said dedicated PADD logic device to perform a packet addition of said first and second operands with a carry in to generate said result.
 7. The method of claim 1, wherein said PADD instruction includes a data field parameter to indicate that only certain bits of the content stored in said first register serves as said first operand.
 8. The method of claim 1, wherein said PADD instruction includes an immediate value parameter to indicate that an immediate value serves as said second operand.
 9. An apparatus comprising: a result register; a first source register; an instruction control device to receive a PADD instruction comprising a result register identifier to identify said result register, a first source register identifier to identify said first source register storing a first operand, and an operand identifier to identify a second operand; and a dedicated PADD logic device responsive to said instruction control device to perform a packet addition of the first and second operands to generate a result subsequently stored in said result register.
 10. The apparatus of claim 9, further comprising a second source register, wherein said operand identifier identifies said second source register as storing said second operand.
 11. The apparatus of claim 9, wherein said operand identifier identifies an immediate value to use as said second operand.
 12. The apparatus of claim 9, wherein said PADD instruction further comprises a start identifier to identify the start bit of said first operand.
 13. The apparatus of claim 9, wherein said PADD instruction further comprises a stop identifier to identify the stop bit of said first operand.
 14. The apparatus of claim 9, wherein said PADD instruction includes a carry in parameter to cause said dedicated PADD logic device to perform a packet addition of said first and second operands with a carry in to generate said result.
 15. The apparatus of claim 9, wherein said PADD instruction includes a data field parameter to indicate that only certain bits of the content stored in said first register serves as said first operand.
 16. The apparatus of claim 9, wherein said PADD instruction includes an immediate value parameter to indicate that an immediate value serves as said second operand.
 17. A method comprising: receiving a SMAD instruction comprising a result register identifier to identify a result register, a first source register identifier to identify a first source register storing a first operand, and a second source register identifier to identify a second source register storing a second operand; and in response to receiving said SMAD instruction, causing a dedicated SMAD logic device to perform an addition of the first and second operands to generate a result, and to subsequently store the result in said result register.
 18. The method of claim 17, wherein said SMAD instruction includes an accumulate parameter that causes the result generated by the SMAD logic device to be added to an existing content of said result register.
 19. The method of claim 17, wherein said SMAD instruction further comprises a 2^(n)−1 modulo parameter to cause said SMAD logic device to perform a 2^(n)−1 modulo addition of said first and second operands.
 20. The method of claim 17, wherein said SMAD instruction further comprises a length parameter to specify the bit length of said first and second operands.
 21. The method of claim 17, wherein said SMAD instruction includes a number of operands parameter to specify the number of operands including the first and second operands which said SMAD logic device is to perform an addition to generate said result.
 22. An apparatus comprising: a result register; a first source register; a second source register; an instruction control device to receive a SMAD instruction comprising a result register identifier to identify said result register, a first source register identifier to identify said first source register storing a first operand, and a second source register identifier to identify said second source register storing a second operand; and a dedicated SMAD logic device responsive to said instruction control device to perform an addition of the first and second operands to generate a result which is subsequently stored in said result register.
 23. The apparatus of claim 22, wherein said SMAD instruction includes an accumulate parameter that causes the result generated by the dedicated SMAD logic device to be added to an existing content of said result register.
 24. The apparatus of claim 22, wherein said SMAD instruction further comprises a 2^(n)−1 modulo parameter to cause said dedicated SMAD logic device to perform a 2^(n)−1 modulo addition of said first and second operands.
 25. The apparatus of claim 22, wherein said SMAD instruction further comprises a length parameter to specify the bit length of said first and second operands.
 26. The apparatus of claim 22, wherein said SMAD instruction includes a number of operands parameter to specify the number of operands including the first and second operands which said dedicated SMAD logic device is to perform an addition to generate said result.
 27. A method comprising: receiving a first source packet comprising a first source data field situated at the least significant bits of said first source packet, a second source data field adjacent to and on a more significant bit side of said first source data field, and a third source data field adjacent to and on a more significant bit side of said second source data field; receiving a second source packet comprising a fourth source data field situated at the least significant bits of said second source packet; and forming a result packet comprising a first result data field being the same bitwise and bit position as said first source data field, a second result data field being the addition of said second and fourth source data fields in the same bit position as said second source data field, and a third result data field being the same bitwise and bit position as said third source data field.
 28. The method of claim 27, wherein forming said result packet comprises: forming a first intermediate packet comprising a first intermediate data field being all non-asserted bits in the same bit position and length as said first source data field, a second intermediate data field being the same bitwise as said fourth source data field and in the same bit position as said second source data field, and a third intermediate data field being all asserted bits in the same bit position and length as said third source data field; forming a second intermediate packet comprising a fourth intermediate data field being the same bitwise and bit position as said first source data field, a fifth intermediate data field being the same bitwise and bit position as said second source data field, and a sixth intermediate data field being all non-asserted bits in the same bit position and length as said third source data field; forming a third intermediate packet comprising a seventh intermediate data field being the same bitwise and bit position as said first source data field, and an eighth intermediate data field being the addition of said second and fifth intermediate data fields; forming a fourth intermediate packet comprising a ninth intermediate data field being the same bitwise and bit position as said first source data field, a tenth intermediate data field being the same bitwise and bit position as said eighth intermediate data field, and an eleventh intermediate data field being all non-asserted bits at the same bit position as said third source data field; forming a fifth intermediate packet comprising a twelfth data field comprising all non-asserted bits at the same bit position as said first and second source data fields, and a thirteen data field being the same bitwise and bit position as said third source data field; and forming said result packet from said fourth and fifth intermediate packets.
 29. The method of claim 28, wherein forming said third intermediate packet comprises adding said first and second intermediate packets.
 30. The method of claim 28, wherein forming said result packet comprises bitwise ORing said fourth and fifth intermediate packets.
 31. The method of claim 27, wherein forming said result packet comprises: forming a first intermediate packet comprising a first intermediate data field being all asserted bits in the same bit position and length as said first source data field, a second intermediate data field being the same bitwise as said fourth source data field and in the same bit position as said second source data field, and a third intermediate data field being all asserted bits in the same bit position and length as said third source data field; forming a second intermediate packet comprising a fourth intermediate data field being the same bitwise and bit position as said first source data field, a fifth intermediate data field being the same bitwise and bit position as said second source data field, and a sixth intermediate data field being all non-asserted bits in the same bit position and length as said third source data field; forming a third intermediate packet comprising a seventh intermediate data field being the same bitwise and bit position as said first source data field, and an eighth intermediate data field being the addition of said second and fifth intermediate data fields; forming a fourth intermediate packet comprising a ninth intermediate data field being the same bitwise and bit position as said first source data field, a tenth intermediate data field being the same bitwise and bit position as said eighth intermediate data field, and an eleventh intermediate data field being all non-asserted bits at the same bit position as said third source data field; forming a fifth intermediate packet comprising a twelfth data field comprising all non-asserted bits at the same bit position as said first and second source data fields, and a thirteen data field being the same bitwise and bit position as said third source data field; and forming said result packet from said fourth and fifth intermediate packets.
 32. The method of claim 31, wherein forming said third intermediate packet comprises adding said first and second intermediate packets with a carry in.
 33. The method of claim 31, wherein forming said result packet comprises bitwise ORing said fourth and fifth intermediate packets.
 34. An apparatus comprising: a logic device to: receive a first source packet comprising a first source data field situated at the least significant bits of said first source packet, a second source data field adjacent to and on a more significant bit side of said first source data field, and a third source data field adjacent to and on a more significant bit side of said second source data field; receive a second source packet comprising a fourth source data field situated at the least significant bits of said second source packet; and form a result packet comprising a first result data field being the same bitwise and bit position as said first source data field, a second result data field being the addition of said second and fourth source data fields in the same bit position as said second source data field, and a third result data field being the same bitwise and bit position as said third source data field.
 35. The apparatus of claim 34, wherein said logic device comprises: a first sub-logic device to form a first intermediate packet comprising a first intermediate data field being all non-asserted bits in the same bit position and length as said first source data field, a second intermediate data field being the same bitwise as said fourth source data field and in the same bit position as said second source data field, and a third intermediate data field being all asserted bits in the same bit position and length as said third source data field; a second sub-logic device to form a second intermediate packet comprising a fourth intermediate data field being the same bitwise and bit position as said first source data field, a fifth intermediate data field being the same bitwise and bit position as said second source data field, and a sixth intermediate data field being all non-asserted bits in the same bit position and length as said third source data field; a third sub-logic device to form a third intermediate packet comprising a seventh intermediate data field being the same bitwise and bit position as said first source data field, and an eighth intermediate data field being the addition of said second and fifth intermediate data fields; a fourth sub-logic device to form a fourth intermediate packet comprising a ninth intermediate data field being the same bitwise and bit position as said first source data field, a tenth intermediate data field being the same bitwise and bit position as said eighth intermediate data field, and an eleventh intermediate data field being all non-asserted bits at the same bit position as said third source data field; a fifth sub-logic device to form a fifth intermediate packet comprising a twelfth data field comprising all non-asserted bits at the same bit position as said first and second source data fields, and a thirteen data field being the same bitwise and bit position as said third source data field; and a sixth sub-logic device to form said result packet from said fourth and fifth intermediate packets.
 36. The apparatus of claim 35, wherein said first sub-logic device comprises: a left shifter to left shift said fourth source data field of said second source packet to the same bit position as said second source data field with leading logic zeros; and a bitwise OR logic device to bitwise OR said shifted source packet with a mask to form said first intermediate packet.
 37. The apparatus of claim 35, wherein said second sub-logic device comprises a bitwise AND logic device to bitwise AND said first source packet with a mask to form said second intermediate packet.
 38. The apparatus of claim 35, wherein said third sub-logic device comprises an adder to add said first intermediate packet to said second intermediate packet to form said third intermediate packet.
 39. The apparatus of claim 35, wherein said fourth sub-logic device comprises a bitwise AND logic device to bitwise AND said third intermediate packet with a mask to form said fourth intermediate packet.
 40. The apparatus of claim 35, wherein said fifth sub-logic device comprises a bitwise AND to bitwise AND said first source packet with a mask to form said fifth intermediate packet.
 41. The apparatus of claim 35, wherein said sixth sub-logic device comprises a bitwise OR logic device to bitwise OR said fourth and fifth intermediate packets to form said result packet.
 42. The apparatus of claim 34, wherein forming said result packet comprises: a first sub-logic device to form a first intermediate packet comprising a first intermediate data field being all asserted bits in the same bit position and length as said first source data field, a second intermediate data field being the same bitwise as said fourth source data field and in the same bit position as said second source data field, and a third intermediate data field being all asserted bits in the same bit position and length as said third source data field; a second sub-logic device to form a second intermediate packet comprising a fourth intermediate data field being the same bitwise and bit position as said first source data field, a fifth intermediate data field being the same bitwise and bit position as said second source data field, and a sixth intermediate data field being all non-asserted bits in the same bit position and length as said third source data field; a third sub-logic device to form a third intermediate packet comprising a seventh intermediate data field being the same bitwise and bit position as said first source data field, and an eighth intermediate data field being the addition of said second and fifth intermediate data fields; a fourth sub-logic device to form a fourth intermediate packet comprising a ninth intermediate data field being the same bitwise and bit position as said first source data field, a tenth intermediate data field being the same bitwise and bit position as said eighth intermediate data field, and an eleventh intermediate data field being all non-asserted bits at the same bit position as said third source data field; a fifth sub-logic device to form a fifth intermediate packet comprising a twelfth data field comprising all non-asserted bits at the same bit position as said first and second source data fields, and a thirteen data field being the same bitwise and bit position as said third source data field; and a sixth sub-logic device to form said result packet from said fourth and fifth intermediate packets.
 43. The apparatus of claim 42, wherein said third sub-logic device comprises an adder to add said first intermediate packet to said second intermediate packet with a carry in to form said third intermediate packet.
 44. A method, comprising: generating a carry and a save from a plurality of operands; adding the carry and the save together without a carry in to form a first sum; adding the carry and the save together with a carry in to form a second sum; selecting said first sum if a modulo 2^(n) addition is desired; selecting said first sum if a modulo 2 ^(n)−1 addition is desired and said first adding does not generate a carry out; and selecting said second sum if said modulo 2^(n)−1 addition is desired and said first adding does generate a carry out.
 45. The method of claim 44, wherein generating said carry and said save is performed by a carry-save adder.
 46. The method of claim 44, wherein generating said carry and said save comprises: generating first and second intermediate carries; generating first and second intermediate saves; and generating said carry and said save from said first and second intermediate carries and said first and second intermediate saves.
 47. The method of claim 46, wherein generating said first and second intermediate carries is performed by a first level carry-save adder, and wherein generating said carry and said save is performed by a second level carry-save adder.
 48. The method of claim 44, wherein generating said carry and said save comprises: generating first level carries and first level saves; generating second level carries and second level saves from said first level carries and first level saves; and generating said carry and said save from said second level carries and second level saves.
 49. The method of claim 48, wherein generating said first level carries and first level saves are performed by a first level carry-save adder, wherein generating said second level carries and second level saves are performed by a second level carry-save adder, and wherein generating said carry and said save is performed by a third level carry-save adder.
 50. The method of claim 44, wherein adding the carry and the save together to form a first sum and adding the carry and the save together with a carry in to form a second sum are performed substantially in parallel.
 51. The method of claim 44, wherein selecting said first sum or said second sum is performed by a multiplexer.
 52. An apparatus, comprising: a carry-save adder to generate a carry and a save from a plurality of operands; a first adder to generate a first sum of said carry and said save, wherein said first adder has a non-asserted carry in; a second adder to generate a second sum of said carry and said save, wherein said second adder has an asserted carry in; and a multiplexer to select as its output said first sum or said second sum.
 53. The apparatus of claim 52, wherein said carry-save adder comprises: a first level carry-save adder to generate first and second intermediate carries and first and second intermediate saves from said operands; and a second level carry-save adder to generate said carry and said save from said first and second intermediate carries and said first and second intermediate saves.
 54. The apparatus of claim 52, wherein said carry-save adder comprises: a first level carry-save adder to generate first level carries and first level saves from said operands; a second level carry-save adder to generate second level carries and second level saves from said first level carries and said first level saves; and a third level carry-save adder to generate said carry and save from said second level carries and said second level saves. 